Datasheet
Table Of Contents
- Product Overview
- 1 ESP32-S3 Series Comparison
- 2 Pin Definition
- 3 Functional Description
- 3.1 CPU and Memory
- 3.2 RTC and Low-Power Management
- 3.3 Analog Peripherals
- 3.4 System Components
- 3.5 Digital Peripherals
- 3.5.1 IO MUX and GPIO Matrix
- 3.5.2 Serial Peripheral Interface (SPI)
- 3.5.3 LCD Interface
- 3.5.4 Camera Interface
- 3.5.5 UART Controller
- 3.5.6 I2C Interface
- 3.5.7 I2S Interface
- 3.5.8 Remote Control Peripheral
- 3.5.9 Pulse Count Controller
- 3.5.10 LED PWM Controller
- 3.5.11 USB 2.0 OTG Full-Speed Interface
- 3.5.12 USB Serial/JTAG Controller
- 3.5.13 Motor Control PWM (MCPWM)
- 3.5.14 SD/MMC Host Controller
- 3.5.15
- 3.6 Radio and Wi-Fi
- 3.7 Bluetooth LE
- 3.8 Timers and Watchdogs
- 3.9 Cryptography/Security Components
- 3.10 Peripheral Pin Configurations
- 4 Electrical Characteristics
- 5 Package Information
- 6 Related Documentation and Resources
- Revision History
3 Functional Description
3. Functional Description
This chapter describes the functional modules of ESP32-S3.
3.1 CPU and Memory
3.1.1 CPU
ESP32-S3 has a low-power Xtensa
®
dual-core 32-bit LX7 microprocessor with the following features:
• Five-stage pipeline that supports the clock frequency of up to 240 MHz
• 16-bit/24-bit instruction set providing high code density
• 32-bit customized instruction set and 128-bit data bus that provide high computing performance
• Support for single-precision floating-point unit (FPU)
• 32-bit multiplier and 32-bit divider
• Unbuffered GPIO instructions
• 32 interrupts at six levels
• Windowed ABI with 64 physical general registers
• Trace function with TRAX compressor, up to 16 KB trace memory
• JTAG for debugging
3.1.2 Internal Memory
ESP32-S3’s internal memory includes:
• 384 KB ROM: for booting and core functions
• 512 KB onchip SRAM: for data and instructions, running at a configurable frequency of up to 240 MHz
• RTC FAST memory: 8 KB SRAM that supports read/write/instruction fetch by the main CPU (LX7
dual-core processor). It can retain data in Deep-sleep mode
• RTC SLOW Memory: 8 KB SRAM that supports read/write/instruction fetch by the main CPU (LX7
dual-core processor) or coprocessors. It can retain data in Deep-sleep mode
• 4 Kbit eFuse: 1792 bits are reserved for user data, such as encryption key and device ID
• SiP flash and PSRAM: See details in Table 1 Comparison
3.1.3 External Flash and RAM
ESP32-S3 supports SPI, Dual SPI, Quad SPI, Octal SPI, QPI and OPI interfaces that allow connection to multiple
external flash and RAM.
The external flash and RAM can be mapped into the CPU instruction memory space and read-only data memory
space. The external RAM can also be mapped into the CPU data memory space. ESP32-S3 supports up to 1
GB of external flash and RAM, and hardware encryption/decryption based on XTS-AES to protect users’
programs and data in flash and external RAM.
Through high-speed caches, ESP32-S3 can support at a time up to:
• External flash or RAM mapped into 32 MB instruction space as individual blocks of 64 KB
Espressif Systems 25
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ESP32-S3 Series Datasheet v1.2