Datasheet
Table Of Contents
- Product Overview
- 1 ESP32-S3 Series Comparison
- 2 Pin Definition
- 3 Functional Description
- 3.1 CPU and Memory
- 3.2 RTC and Low-Power Management
- 3.3 Analog Peripherals
- 3.4 System Components
- 3.5 Digital Peripherals
- 3.5.1 IO MUX and GPIO Matrix
- 3.5.2 Serial Peripheral Interface (SPI)
- 3.5.3 LCD Interface
- 3.5.4 Camera Interface
- 3.5.5 UART Controller
- 3.5.6 I2C Interface
- 3.5.7 I2S Interface
- 3.5.8 Remote Control Peripheral
- 3.5.9 Pulse Count Controller
- 3.5.10 LED PWM Controller
- 3.5.11 USB 2.0 OTG Full-Speed Interface
- 3.5.12 USB Serial/JTAG Controller
- 3.5.13 Motor Control PWM (MCPWM)
- 3.5.14 SD/MMC Host Controller
- 3.5.15
- 3.6 Radio and Wi-Fi
- 3.7 Bluetooth LE
- 3.8 Timers and Watchdogs
- 3.9 Cryptography/Security Components
- 3.10 Peripheral Pin Configurations
- 4 Electrical Characteristics
- 5 Package Information
- 6 Related Documentation and Resources
- Revision History
2 Pin Definition
Pin Default
EFUSE_DIS_USB_JTAG = 0, EFUSE_DIS_PAD_JTAG = 0,
EFUSE_STRAP_JTAG_SEL=1
GPIO3 N/A
0: JTAG signal from on-chip JTAG pins
1: JTAG signal from USB Serial/JTAG controller
Note:
1. The strapping combination of GPIO46 = 1 and GPIO0 = 0 is invalid and will trigger unexpected behavior.
2. By default, the ROM boot messages are printed over UART0 (U0TXD pin) and USB Serial/JTAG controller together.
The ROM code printing can be disabled through configuration register and eFuse. For detailed information, please
refer to Chapter Chip Boot Control in ESP32-S3 Technical Reference Manual.
VDD_SPI voltage is determined either by the strapping value of GPIO45 or by EFUSE_VDD_SPI_TIEH. When
EFUSE_VDD_SPI_FORCE is 0, VDD_SPI voltage is determined by the strapping value of GPIO45; when
EFUSE_VDD_SPI_FORCE is 1, VDD_SPI voltage is determined by EFUSE_VDD_SPI_TIEH. Please refer to the
following table for default configurations:
Table 10: The Default Value for VDD_SPI Voltage
Chip Variant EFUSE_VDD_SPI_FORCE EFUSE_VDD_SPI_TIEH VDD_SPI Voltage
ESP32-S3 0 0 Determined by GPIO45
ESP32-S3R2 1 1 Force to 3.3 V
ESP32-S3R8 1 1 Force to 3.3 V
ESP32-S3R8V 1 0 Force to 1.8 V
ESP32-S3FN8 1 1 Force to 3.3 V
ESP32-S3FH4R2 1 1 Force to 3.3 V
Figure 6 shows the setup and hold times for the strapping pin before and after the CHIP_PU signal goes high.
Details about the parameters are listed in Table 11.
CHIP_PU
t
HD
t
SU
Strapping pin
V
IL_nRST
V
IH
Figure 6: Setup and Hold Times for the Strapping Pin
Espressif Systems 23
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ESP32-S3 Series Datasheet v1.2