Datasheet
Table Of Contents
- Product Overview
- 1 ESP32-S3 Series Comparison
- 2 Pin Definition
- 3 Functional Description
- 3.1 CPU and Memory
- 3.2 RTC and Low-Power Management
- 3.3 Analog Peripherals
- 3.4 System Components
- 3.5 Digital Peripherals
- 3.5.1 IO MUX and GPIO Matrix
- 3.5.2 Serial Peripheral Interface (SPI)
- 3.5.3 LCD Interface
- 3.5.4 Camera Interface
- 3.5.5 UART Controller
- 3.5.6 I2C Interface
- 3.5.7 I2S Interface
- 3.5.8 Remote Control Peripheral
- 3.5.9 Pulse Count Controller
- 3.5.10 LED PWM Controller
- 3.5.11 USB 2.0 OTG Full-Speed Interface
- 3.5.12 USB Serial/JTAG Controller
- 3.5.13 Motor Control PWM (MCPWM)
- 3.5.14 SD/MMC Host Controller
- 3.5.15
- 3.6 Radio and Wi-Fi
- 3.7 Bluetooth LE
- 3.8 Timers and Watchdogs
- 3.9 Cryptography/Security Components
- 3.10 Peripheral Pin Configurations
- 4 Electrical Characteristics
- 5 Package Information
- 6 Related Documentation and Resources
- Revision History
2 Pin Definition
• GPIO0
• GPIO45
• GPIO46
• GPIO3
Software can read the values of corresponding bits from register “GPIO_STRAPPING”.
During the chip’s system reset (power-on-reset, RTC watchdog reset, brownout reset, analog super watchdog
reset, and crystal clock glitch detection reset), the latches of the strapping pins sample the voltage level as
strapping bits of “0” or “1”, and hold these bits until the chip is powered down or shut down.
GPIO0, GPIO45 and GPIO46 are connected to the chip’s internal weak pull-up/pull-down during the chip reset.
Consequently, if they are unconnected or the connected external circuit is high-impedance, the internal weak
pull-up/pull-down will determine the default input level of these strapping pins.
GPIO3 is floating by default. Its strapping value can be configured to determine the source of the JTAG signal
inside the CPU, as shown in Table 9. In this case, the strapping value is controlled by the external circuit that
cannot be in a high impedance state. Table 8 shows more configuration combinations of
EFUSE_DIS_USB_JTAG, EFUSE_DIS_PAD_JTAG, and EFUSE_STRAP_JTAG_SEL that determine the JTAG
signal source.
Table 8: JTAG Signal Source Selection
EFUSE_STRAP_JTAG_SEL EFUSE_DIS_USB_JTAG EFUSE_DIS_PAD_JTAG JTAG Signal Source
1 0 0 Refer to Table 9
0 0 0 USB Serial/JTAG controller
don’t care 0 1 USB Serial/JTAG controller
don’t care 1 0 On-chip JTAG pins
don’t care 1 1 N/A
To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or use the host
MCU’s GPIOs to control the voltage level of these pins when powering on ESP32-S3.
After reset, the strapping pins work as normal-function pins.
Refer to Table 9 for a detailed configuration of the strapping pins.
Table 9: Strapping Pins
VDD_SPI Voltage
Pin Default 3.3 V 1.8 V
GPIO45 Pull-down 0 1
Booting Mode
1
Pin Default SPI Boot Download Boot
GPIO0 Pull-up 1 0
GPIO46 Pull-down Don’t care 0
Enabling/Disabling ROM Messages Print During Booting
2
Pin Default Enabled Disabled
GPIO46 Pull-down See the 2nd note See the 2nd note
JTAG Signal Selection
Espressif Systems 22
Submit Documentation Feedback
ESP32-S3 Series Datasheet v1.2