Datasheet

Product Overview
ESP32-S3 is a low-power MCU-based system-on-chip (SoC) that supports 2.4 GHz Wi-Fi and Bluetooth
®
Low
Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor (Xtensa
®
32-bit LX7), a low
power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, RF module, and peripherals. The block
diagram of the SoC is shown below.
Core System
Wireless MAC and
Baseband
Wi-Fi MAC
Wi-Fi
Baseband
Bluetooth LE Link Controller
Bluetooth LE Baseband
2.4 GHz Balun + Switch
2.4 GHz
Receiver
2.4 GHz
Transmitter
RF Synthesizer
RF
Security
Xtensa
®
Dual-core
32-bit LX7
Microprocessor
JTAG
Cache
Flash
Encryption
Peripherals
Espressif’s ESP32-S3 Wi-Fi + Bluetooth
®
Low Energy SoC
ROM
SRAM
RSA
RNG
Digital
Signature
SHA
AES
HMAC
Secure
Boot
USB Serial/
JTAG
GPIO
UART
SDIO Host
TWAI
®
General-
purpose Timers
GDMA
I2S
LCD
Interface
I2C
MCPWM
Pulse Counter
USB OTG LED PWM
Camera
Interface
SPI0/1
RMT
SPI2/3
DIG ADC
Controller
Watchdog
Timers
System
Timers
RTC GPIO
Touch Sensor
Temperature
Sensor
RTC ADC
Controller
RTC
Memory
RTC
Watchdog
Timer
RTC
Modules having power in specific power modes:
Active
Active and Modem-sleep
all modes;
Active, Modem-sleep, and Light-sleep; optional in Light-sleep
⚙
PMU
eFuse
Controller
ULP
Coprocessor
optional in Deep-sleep
⚙
⚙
⚙
⚙
⚙
⚙
RTC I2C
⚙
⚙
⚙
⚙
⚙
⚙
⚙
⚙
⚙
⚙
⚙
⚙
Figure 1: Block Diagram of ESP32S3
Solution Highlights
• A complete WiFi subsystem that complies
with IEEE 802.11b/g/n protocol and supports
Station, SoftAP, and SoftAP + Station modes
• A Bluetooth LE subsystem that supports
features of Bluetooth 5 and Bluetooth mesh
• Xtensa
®
32bit LX7 dualcore processor with
a five-stage pipeline that operates at up to 240
MHz
– A 128-bit data bus and dedicated SIMD
instructions to provide high computing
Espressif Systems 2
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ESP32-S3 Series Datasheet v1.2