Datasheet

2 Pin Definition
Type
Each digital function (Fn, n=0~4) is associated with a “Type”. The description of “Type” is as follows:
• O: Output only.
• O/T: The signal can be output or high-impedance.
• I/O/T: The signal can be input, output, and high-impedance.
• I1: Input only. If the pin is assigned a function other than Fn, the input signal of Fn is always “1”.
• I1/O/T: The signal can be input, output, and high-impedance. If Fn is not selected, the input signal of Fn is
always “1”.
• I0/O/T: The signal can be input, output, and high-impedance. If Fn is not selected, the input signal of Fn is
always “0”.
At Reset/After Reset
The default configuration of each pin at reset and after reset:
• IE0 - input disabled
• IE1 - input enabled
• IE1, WPD1 - input enabled, internal weak pull-down resistor enabled
• IE1, WPU1 - input enabled, internal weak pull-up resistor enabled
• IE1, or IE1&WPU1 - When the value of eFuse bit EFUSE_DIS_PAD_JTAG is
1, the MTCK pin floats after chip reset (IE1)
0, the MTCK pin connects to internal weak pull-up resistor after chip reset (IE1&WPU1)
Notes
• R - These pins have RTC or analog functions.
Drive Strength
• The default drive strength of GPIO19 ~ 20 is 2’d3 (~40 mA).
• The default drive strength of other pins is 2’d2 (~20 mA).
2.6 PintoPin Mapping Between Chip and SiP Flash/PSRAM
Table 6 lists the pin-to-pin mapping between the chip and the SiP flash/PSRAM. The chip pins listed here are not
recommended for other usage. For the data port connection between ESP32-S3 and external flash please refer
to Section 3.5.2.
Table 6: PintoPin Mapping Between Chip and SiP Flash/PSRAM
ESP32S3FN8 (8 MB) / ESP32S3FH4R2 (4 MB) SiP Flash (Quad SPI)
SPICLK CLK
SPICS0 CS#
SPID DI
SPIQ DO
SPIWP WP#
SPIHD HOLD#
Espressif Systems 19
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ESP32-S3 Series Datasheet v1.2