Specifications

Table Of Contents
MAINTENANCE
Page 119 MRC-565 Packet Data Radio Operations & Maintenance
is used to break out the discrete digital output, relay junction and analog input ports into one D-
25 pin connector. The user can program these inputs and outputs to execute timed events or to
monitor external asynchronous events.
6.1.5 Power Amp Interface
The CMU interfaces to the RFPA assembly via 4 cables. CMU J15 connects to the RFPA with a
20-pin ribbon cable. RX RF coaxial cable from the RFPA enters the CMU at J1. The TX exciter
output to the RFPA is at J16. The optional GPS receiver input to the CMU is at J4.
Nominal 12V DC power for the CMU is obtained from the RFPA assembly via J15.
6.2 Microprocessor
This section outlines the general computer architecture for the MRC-565 microprocessor board.
Detailed sections are supplied describing the power, processor, memory, and I/O subsystems.
Discussion of the microprocessor includes:
Overview
CPU
Memory
Data Input/Output
Discrete Digital Output, Relay junctions and Analog to Digital Input
Transmitter/Receiver Interface
Peripherals
Power Fail Detection/Protection
DSP BPSK I & Q Generator
6.2.1 Overview
The MRC-565 microprocessor board contains a small, low power, industrial grade
microcontroller (the Motorola MC68332 processor) surrounded with memory, I/O, and
peripherals to meet the requirements for the MRC-565.
The basic unit contains:
Motorola MCF 54455 Coldfire microprocessor
External RS 232 I/O ports (+/- 5V), quantity 3
Internal serial port1(jp3 selectable) , serial port 2 (jp4 selectable), or port 3 I2C for GPS
(0 to 5V), quantity 1
Power Amplifier Interface Port
Real-time clock