Specifications

MAINTENANCE
Page 118 MRC-565 Packet Data Radio Operations & Maintenance
Gaussian low pass pulse filter is used to spectrally limit the pulse train so that it fits inside FCC
spectral emission mask C. The sum of the filter coefficients is scaled to equal exactly 180
degrees of phase shift. The sine and cosine of the phase are determined from LUTs. The resulting
I and Q samples are then transferred to the FPGA TX FIFO.
6.1.3.3.3 Constant Envelope GMSK Modulation
Minimum shift keying (MSK) is a form of FSK where the peak-to-peak frequency deviation is
exactly one half of the bit rate and the peak deviation is therefore one fourth the bit rate. The
carrier phase of unfiltered MSK snaps forward or back 90 degrees each bit period. There is no
AM. A Gaussian LPF is added to smooth the step response to bit polarity changes and reduce the
spectral bandwidth. The MRC565 GLPF uses BT = 1 meaning that the 3dB BW equals the bit
rate. This mild filtering is suitable for meeting FCC spectral emission mask C at 9600 bps or
less. A LUT is used to provide the filter response for the samples in one bit period based on the
values of the current bit and the previous bit. The filter output represents a phase increment. This
is accumulated to produce phase rotation (relative to unmodulated carrier phase) for each sample.
A sin LUT is used to obtain the sin and cos of the phase. These values are entered into the I/Q
sample buffers for transmission to the FPGA TX FIFO.
6.1.3.3.4 Downstream Transmit Sample Processing
The DSP output I and Q baseband modulation sample rate is 96 ksps. These samples must be
further interpolated to the digital modulator sample rate to avoid modulation aliases. The FPGA
is used to provide sample rate interpolation by a factor of 25 to 2.4 Msps. The 2.4 MHz I and Q
samples are interleaved for transfer to the QDUC. The QDUC provides the final interpolation by
200 to 480 Msps.
6.1.3.4 Modulation Limiting
In either modulation type, the DSP calculations are precise and well-behaved. This is one way
that transmitter spectral control is achieved. Digital signal processing and accurate clock sources
produce baseband modulation signal waveforms that have precisely controlled amplitude and
spectral characteristics described above. These levels and spectral characteristics are fixed by
firmware and require no further calibration or adjustment prior to the modulator.
6.1.3.5 Power Limiting
The Transmitter Block Diagram, Figure 16, shows that the RF power amplifier (RF PA) has an
average power output detector and DC feedback system to control the gain of one of the RF
amplifier stages. This provides automatic level control to stabilize transmitter power output over
rated temperature and power supply voltage ranges. The feedback is adjusted to set the RF output
power to 100W at the programmed operating frequency at time of order processing. The power
detector variation over the programmable transmitter frequency range is less than 1 dB.
A hardware duty cycle limiter in the PA relies on a fixed RC time constant to cut off power to
the RF amplifiers to protect them against overheating as well as functioning as a backup to the
OS duty cycle limiting algorithm.
6.1.4 Discrete Digital Output, Relay Junction and Analog Input
Four optically isolated inputs, two form “C” 2 amp relays and six 10-bit Analog to Digital
converter channels are routed through a high density D-44 pin connector. A 4 lead adapter cable