Specifications

MAINTENANCE
Page 117 MRC-565 Packet Data Radio Operations & Maintenance
QDUC PLL lock condition is monitored by the OS. The OS will abort or inhibit transmission if
the QDUC PLL is unlocked.
The NCO output samples are applied to sine and cosine digital lookup tables. The sine and
cosine signals are applied to a complex digital modulator operating at 480 Msps, also inside the
QDUC. The modulator output is applied to a high speed DAC and then exits the QDUC as an
approximate 1 mW modulated RF carrier. A 7-pole LC low pass filter then removes the 400+
MHz alias frequency output and other minor QDUC intermodulation products before the signal
is routed to the RFPA.
Details of the carrier modulation process are provided below.
6.1.3.2 RF Power Amplifiers
The low level modulated carrier is passed to the RFPA circuit board where it is amplified to
10W, 25W, 50W or 100W by three RF amplifiers in a chain depending on operator selection.
One inter-stage low pass filter and final output low pass filter as well as frequency selective
components not shown remove harmonics created by the nonlinearity of the RF amplifiers.
Automatic output power level control (ALC) is provided by a feedback loop as shown on the
RFPA diagram. This keeps output power stable over a range of power supply voltages and
operating temperatures.
6.1.3.3 Modulation Process
NRZ user data enters the MRC-565 via a serial, USB or Ethernet port. The OS packetizes it and
adds preamble, synch, protocol headers and checksums. Packets will vary in length from
approximately 20 ms to 200 ms. The transmitter can emit either constant envelope (CE) BPSK or
CE GMSK.
6.1.3.3.1 CF and DSP TX Character processing
The CF assembles all of the header, payload and CRCC bytes of the message packet. The CF
(including the CPLD glue logic) also orchestrates the TX start up and shut off control and
sequencing. There is one message packet per transmission in half duplex mode. The CF uses the
DSP HPI to transfer the TX character bytes to the DSP TX message FIFO buffer.
The DSP is responsible for modulation pre-coding, band limiting and part of the sample rate
interpolation process. Packet Characters are block processed, one byte, i.e., 8 bits at a time. The
packet bits are sent serially, one bit per symbol so the bytes are first disassembled into individual
bits.
The DSP converts the message data bytes first to bipolar bits and then concatenates bits from
consecutive bytes into a continuous stream. Each modulation type is further described below.
6.1.3.3.2 Constant Envelope Differentially Encoded BPSK Modulation
Differentially encoded BPSK is confined to a circular phase trajectory so it has fixed amplitude,
i.e., no amplitude modulation (AM). Each new bit is converted to a bipolar value dependent on
the previous bit. If the result is positive (negative), the phase of the carrier will be advanced
(retarded) 180 degrees during the bit period. If the result is 0, the carrier phase is not affected. A