Specifications

Page 113 MRC-565 Packet Data Radio Operations & Maintenance
The DSP processes each sample block while the next block is being collected. A separate section
discusses the multi-simultaneous channel capability of the receiver.
The sample block transfer and demodulation process is normally gated by the presence of a
signal present (SP) average power detector that is implemented in the FPGA. User settable
parameters determine the power level required in the receive channel to cross the SP threshold
and this activates the FPGA to DSP sample block transfers. A later section discusses how
features such as this are part of the low power modes (LPM) contribute to reducing the average
receiving DC power dissipation while the receiver idles.
The DSP BPSK demodulator uses a squaring loop digital PLL to recover the estimated receiver
carrier. This facilitates coherent detection of the BPSK samples. The symbol timing is also
recovered. Data bits are recovered by hard decision sampling at the symbol (bit) rate. Note that
for BPSK the symbol, baud and bit rates are all the same value. The bits are initially applied to a
digital correlator that searches for the 24 bit synchronization (sync) word. When sync is
detected, the DSP SP signal going to the CPLD is set high. This signal is needed to wake up the
CF when it is sleeping in low power mode. DSP SP can be viewed at TP9.
The balance of the bits in the received packet are funneled into message bytes and entered into a
receiver buffer in the DSP. It also notifies the CF via the HP_/HINT (TP33) that data packet
bytes are available for collection via the host port interface (HPI) between the DSP and CF.
The DSP can alternately demodulate 9.6 kbps GMSK packets. GMSK is a variation of FSK. The
I and Q sample blocks are applied to a digital limiter and frequency discriminator. The
discriminator is implemented by a delay-conjugate-multiply plus arctan algorithm. Its output is
applied to a sync correlator that detects the sync bytes as well as determining the optimum hard
decision sampling instant for the following packet bits. Operation past that point is the same as
BPSK.
6.1.2.6 Detected RF signal power (DETRF)
As mentioned earlier, the FPGA measures the noise and signal power in the signal channel,
converts it to decibel values and passes the value to the DSP every 2.08 ms. The DSP applies a
factory gain calibration factor called ADCGAIN to determine the absolute power level in dBm.
This is reported as DETRF value via HPI to the CF (and is also known as received signal
strength indicator RSSI) value that can be viewed by various commands such as MM or STAT.
The value is also converted to a scale that drives one channel of the octal utility DAC U83 over a
range of zero to five volts. The DAC output is routed to J7, the 40-pin front panel connector for
viewing with a scope or voltmeter.