Specifications

Page 112 MRC-565 Packet Data Radio Operations & Maintenance
to 50 MHz. The U85 internal VCO operates at ten times the output frequency. The sampling
clock applied to the ADC can be viewed at TP86. The main processor monitors the U85 lock
condition via bit 13 of CPLD input register A. If unlock is detected, the synthesizer will be
reloaded.
6.1.2.4 Field Programmable Gate Array – Receiving Logic
The 14-bit ADC output samples representing the analog signals in the 40 to 43 MHz tuning
range are input to the field programmable gate array (FPGA) EP3C10 U37. The FPGA contains
programmable logic hardware used in the receiver (as well as other logic used in the transmitter).
It is well suited to very high speed dedicated repetitive tasks needed for digital reception and
transmission. The FPGA logic functions are booted by loading compiled hardware description
language (HDL) code into it at time of radio initialization.
The FPGA contains digital mixer, digital tunable oscillator, baseband digital channel width band
pass I and Q filters that also decimate the sample rate to lower values. Digital RMS signal power
detectors and automatic gain control (AGC) are also included. AGC is necessary to compress the
full dynamic range of the receiver into convenient16-bit wide output samples. The first digital
intermediate frequency is from approximately 6 (= 40-34) to 9 (= 43-34) MHz. The digital mixer
output is baseband (or zero intermediate frequency) I and Q channels.
The other input to the digital mixer is from a direct digital synthesizer (DDS) numerically
controlled oscillator (NCO). The NCO operates at the ADC sample rate and synthesizes the
tuning frequency using an accumulator followed by sine and cosine lookup tables. For example,
if the desired receiver frequency is 40.000 MHz, the first IF is 5.920 MHz and the NCO is tuned
to 5.920 MHz to translate the desired signal channel carrier frequency to exactly 0 Hz baseband.
The signal in the desired 10 kHz bandwidth RF channel is represented by two 5 kHz low pass
signals in quadrature phase relationship with each other, known as I (in-phase) and Q
(quadrature-phase) digital channels. The sample rate is ultimately reduced to 48 ksps in each
channel by the low pass decimator filters following the digital mixer. This rate still greatly
exceeds the Nyquist rate for 5 kHz I and Q signal bandwidth at the FPGA output. The filtering
and sample rate decimation provide a crucial signal to noise ratio (SNR) enhancement (also
known as signal processing gain) that increases the SNR by more than 30 dB to overcome the
high 38 dB effective noise figure of the ADC input.
6.1.2.5 DSP demodulator
The 48 ksps I and Q samples are transferred from the FPGA into the DSP working memory by
its direct memory access (DMA) controller. The TMS320VC5510A DSP is 16-bit fixed point
numeric implementation with internal program and data memory RAM. The DSP program is
written in compiled C language that is loaded into the DSP by the CF at time of radio
initialization.
The receiving samples are bundled in blocks of one hundred; one block is transferred every 2.08
ms. The FPGA notifies the DSP through an external interrupt when a block of samples is ready.