Specifications

Page 111 MRC-565 Packet Data Radio Operations & Maintenance
-24 dBm. Note that the radio continues to receive strong desired signals on up to +10 dBm or
more but any off-channel signals in the RF pass band stronger than -24 dBm will block desired
signals.
6.1.2 Digital Receiver Components
6.1.2.1 Analog to Digital Converter
The LTC2256 high speed ADC (U71) marks the input point of the digital signal processing
elements that function as the digital receiver and digital demodulator. It directly affects several
of the receiver performance parameters such as noise figure, dynamic range and sensitivity. The
ADC quantizes the analog input into discrete samples at a 34.08 MHz sample rate for receiver
frequencies between 40 and 43 MHz. Each quantized sample is converted to a 14-bit signed
digital word. Signal processing power consumption is directly proportional to sample rate. ADC
and subsequent receiver processing elements’ power consumption is directly proportional to the
sampling rate. There is an obvious incentive to keep it as low as possible but this must be traded
off with the required receiver front end bandwidth and the complexity of the analog filters that
are required to eliminate unwanted signals related to the sampling frequency. The sampling
frequency must also exceed the Nyquist rate, i.e., it must be a factor several times the
approximately 5 MHz band pass filter bandwidth. The maximum differential voltage input to the
ADC is 2 volts p-p. This level is the equivalent of a 10 dBm signal in a 50 ohm system. Signals
greater than this level will saturate the DSP, meaning they will be clipped at the DSP input. (The
ADC internal design avoids arithmetic overflow.) Saturation is allowed for a strong desired
signal because only the signal phase must be preserved for demodulation of BPSK and GMSK. If
the saturating signal is off-channel, the receiver will be blocked. The digital output of the ADC is
2’s complement format but it is pseudo-randomized to avoid large supply current spikes when
signals are near zero level. Such spikes can feed back to the ADC analog input and reduce its
sensitivity. The ADC sampling clock is also passed to the FPGA to allow proper registration.
The FPGA removes the pseudo randomness.
6.1.2.2 Temperature Compensated Crystal Oscillator (TCXO)
The master frequency and clock reference for the transmitter and receiver is the 19.2 MHz
TCXO. It is designed to maintain frequency stable to ±2.5 ppm over the -40° to +85° C
temperature range. It’s actual frequency stability over the rated temperature range of the radio is
typically ±1 ppm. The TCXO has a voltage input that allows calibrating its room temperature
frequency to within a few Hertz of 19.2 MHz. The DSP receives the factory calibration factor
from the CF via the host port interface and applies it to channel 0 of the octal utility DAC. This
DAC voltage fine tunes the TCXO to the desired frequency. The TCXO output is buffered by
U52, U59 and U87 to drive the precision reference clock to the receiver clock synthesizer, the
transmitter clock synthesizer, the FPGA and the DSP.
6.1.2.3 Receiver Clock Synthesizer
The RX clock synthesizer is an ADF4360-9, U85. It is programmed to lock its VCO to 17.75
times its 19.2 MHz TCXO input, then divides it by 10 to 34.08 MHz. The internal VCO of the
ADF4360-9 has a single sideband phase noise characteristic that is low enough to meet the
receiver adjacent channel protection ratio (RX ACPR) specification. The RX clock can also be
set to three higher frequencies 36.00, 37.92 and 39.84 MHz for higher receiver tuning ranges up