Specifications

Page 110 MRC-565 Packet Data Radio Operations & Maintenance
6 THEORY OF OPERATION
The MRC-565 Packet Data Radio contains the Communications Management Unit (CMU) and
The Power Amplifier (PA) printed circuit board assemblies. An optional GPS receiver can also
be provided. This GPS solders onto the CMU and is done at the factory. These assemblies are
discussed in the following paragraphs. The text references parts that can be located on the block
diagrams and printed circuit board assembly drawings given below.
6.1 CMU (MRC-56500300-04)
The CMU is located on a single 8.5" x 3.5" printed circuit board
Discussion of the CMU includes:
 Receiver Analog Front End
 Digital Receiver Components
 ADC LTC2256
 19.2 MHZ TCXO
 RX Clock Generator ADF4360
 FPGA
 DSP
 DAC
 Digital Transmitter Components
 Quadrature Digital Up Converter QDUC AD 9957
 Voltage Regulators
 I/O Circuitry
 Coldfire Microprocessor

6.1.1 Receiver Analog Front End
The received RF signal is coupled through the transmit/receive switch (on the power amplifier
PCA) to the receiver input (first) Band pass filter (BPF) at connector J1. The BPF is a 2-section
top-coupled design, with a 40 to 45 MHz pass band. The filter is fixed tuned by using and uses
close tolerance L's and C's.
The first BPF output is amplified 21 dB by RF amplifier SGL0363 MMIC U13. The noise figure
at J1 is about 5 dB and the 3
rd
order intercept point is approximately -20 dBm.
A 3-section LC BPF follows U13 to increase out of band selectivity to reduce receiver
intermodulation products and for anti-alias (image) rejection. A second SGL0363 MMIC RF
amplifier U44 provides additional 21 dB of gain.
The net analog receiver gain between the BNC antenna input jack and the LTC2256 analog to
digital converter (ADC) U71 is ~36 dB. This means ADC input saturation occurs at levels above