Specifications

The staircase generator shown in Figure 19 can be used as
an A-D converter. A suitable configuration is shown in
Fig-
ure 25.
To start a convert cycle the processor generates a
reset pulse to discharge the integrating capacitor C2. Each
complete clock cycle generates a charge and discharge cy-
cle on C1. This results in two steps per cycle being added to
C2. As the voltage on C2 increases, clock pulses are re-
turned to the processor. When the voltage on C2 steps
above the analog input voltage the data line is clamped and
C2 ceases to charge. The processor, by counting the num-
ber of clock pulses received after the reset pulse, is thus
loaded with a digital measure of the input voltage. By mak-
ing C2/C1
e
1024 an 8-bit A-D is obtained.
Input can be
g
20 mV to
g
28V TL/H/7451–41
TL/H/7451–42
Pulse width
e
V
CC
2
c
C1
I
2
Output frequency equal twice input frequency. Pulse width
e
V
CC
2
c
C1
I
2
Pulse height
e
V
ZENER
FIGURE 23. ‘‘Two-Shot’’ Zero Crossing Detector
TL/H/7451–43
TL/H/7451–44
FIGURE 24. Zero Crossing Detector and Line Drivers
TL/H/7451–45
TL/H/7451–46
FIGURE 25. A-D Converter
14