Specifications

The AGP bus is an enhanced PCI bus with extra functionality to burst texture data and other graphics across

the port up to 8 times faster than a 66 MHz PCI port. The Power Mac G5 computer’s AGP implementation is

compatible with version 3 of the AGP specification and with the Pro version of AGP. AGP 3.0 enables deeply

pipelined memory read and write operations and demultiplexing of address and data on the bus.

To further improve the performance of the AGP bus, the U3H IC supports a graphics address remapping table

(GART). Because the virtual memory system organizes main memory as randomly distributed 4 KB pages, DMA

transactions for more than 4 KB of data must perform scatter-gather operations. To avoid this necessity for

AGP transactions, the GART is used by the AGP bridge in the U3H to translate a linear address space for AGP

transactions into physical addresses in main memory.

The U3H IC also supports a DMA Address Relocation Table (DART) that provides the same functions for AGP

as does the GART, except that the functions are for devices attached to HyperTransport. Most device drivers

do not require special knowledge of the DART because IOKit will configure it automatically if the driver uses

IOMemoryDescriptors.

For more information on the graphics cards installed in the AGP slot, refer to Graphics Cards (page 28).

Note: The AGP bus is 1.5 V only and is not backward compatible. Older AGP cards will not work in

the Power Mac G5 computer.

Internal PCI Bus

An internal 33 MHz, 64-bit PCI bus connects the K2 I/O controller to the boot ROM, the AirPort Extreme Card

slot, and the USB controller. The U3H IC used in the Power Mac G5 computer supports the PCI write combining

feature. This feature allows sequential write transactions involving the Memory Write or Memory Write and

Invalidate commands to be combined into a single PCI transaction. For memory write transactions to be

combined, they must be sequential, ascending, and non-overlapping PCI addresses. Placing an eieio or sync

command between the write commands prevents any write combining.

For more information on the PCI bus, refer to PCI or PCI-X Expansion Slots (page 62).

PCI or PCI-X Expansion Slots

In some configurations, the Power Mac G5 computer provides three 64-bit 33 MHz PCI slots that interface to

the K2 I/O and share the bus with the USB controller.

Architecture

Bridge and Memory Controller