Specifications

Bridge and Memory Controller

The U3H custom IC is at the heart of the Power Mac G5 computer. It provides the bridging functionality among

the processors, the memory system, HyperTransport bus to the PCI-based I/O system, and the AGP slot.

Processor Bus

The processor bus is a 1 GHz, 1.15 GHz or 1.35 GHz bus connecting the processor module to the U3H IC. The

bus has 64-bit (32-bit in and 32-bit out) wide data and 36-bit wide addresses.

The Power Mac G5 system controller is built with 130-nanometer, SOI technology. This super-efficient

point-to-point architecture provides each subsystem with dedicated bandwidth to main memory. The Power

Mac G5 uses separate processor boards with each PowerPC G5 processor; two processor boards are used for

the Power Mac G5’s dual processor design. The U3H I/O implements two independent processor interfaces.

The processor clock is derived from a PLL which multiplies the reference clock by preset intervals of 8 times.

Out-of-order completion allows the memory controller to optimize the data bus efficiency by transferring

whichever data is ready, rather than having to pass data across the bus in the order the transactions were

posted on the bus. This means that a fast DDR SDRAM read can pass a slow PCI read, potentially enabling the

processor to do more before it has to wait on the PCI data.

Intervention is a cache-coherency optimization that improves performance for dual-processor systems. If one

processor modifies some data, that data first gets stored only in that processor’s cache. If the other processor

then wants that data, it needs to get the new modified values.

Main Memory Bus

The Power Mac G5 computer main memory bus connects the main memory to the U3H IC via the 128-bit data

bus. The memory modules are 400 MHz (PC3200) DDR SDRAM DIMMs with a per system maximum of 4 GB or

8 GB, depending on the configuration.

Standard supported DIMM sizes are 128, 256, 512 MB, and 1 GB. The DIMMs must be unbuffered and installed

in pairs of the same size.

For more information about memory DIMMs and installation, see RAM Expansion (page 57).

Accelerated Graphics Port Bus

The accelerated graphics port (AGP 8x Pro) bus is a 266/533 MHz, 32-bit bus connecting the AGP card to the

U3H IC. DDR data is transmitted at both edges of the clock for peak transfers of 2.1 GBps.

Architecture

Bridge and Memory Controller