Specifications

Figure 2-2 (page 19) is a simplified block diagram of the dual processor 2.3 and 2.7 GHz Power Mac G5. The
diagram shows the U3H and K2 ICs and the buses that connect them together.
Figure 2-1 block diagram for dual 2.0 GHz configuration
400 MHz
DDR memory bus
DIMM slots
PCI slots
64-bit
33 MHz
PCI
10/100/1000
Ethernet port
Optical digital audio out
AirPort antenna port
Processor interface bus
running at half the
processor speed
Optical digital audio in
FireWire 400 port (front)
33 MHz
PCI bus
8X AGP-Pro
slot 2.1 GBps
Boot
ROM
I2S
USB 2.0 port- (front)
480 Mbps
USB 2.0 port (rear)
480 Mbps
USB 2.0 port (rear)
480 Mbps
FireWire 400 port (rear)
FireWire 800 port (rear)
Main logic board
Internal
speaker
AirPort Extreme
Card slot
Headphone jack
Audio line-out port
Audio line-in port
FireWire
PHY
Audio
circuitry
PCI USB
controller
12 Mbps
USB
Bluetooth Bluetooth antenna port
Processor moduleProcessor module
64-bit PowerPC G5
microprocessor
64-bit PowerPC G5
microprocessor
8-bit
1.6 GBps
Hyper
Transport
U3H
memory
controller
and PCI
bus bridge
1.5 Gbps
Serial ATA bus
PMU99
power
controller
Modem slot
Internal hard drive
connectors
ATA/100 bus
I2S
1.5 Gbps
Serial ATA bus
Internal optical
drive connector
K2
I/O device
and disk
controller
Architecture
Block Diagram and Buses
Retired Document | 2005-04-29 | Copyright © 2003, 2005 Apple Computer, Inc. All Rights Reserved.
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