Specifications

CHAPTER 4
Expansion Features
The DAV Connector 57
Table 4-10 gives descriptions of the signals on the DAV connector.
Signal Levels 4
When designing PCI card hardware to support the DAV connection, observe these rules:
■ Connect a 47 Ω resistor in series between the bidirectional signals of the DAV
connector and any PCI expansion card circuitry that drives output or bidirectional
signals. This rule applies to pins 11 through 26, 28, 30, 32, and 36.
■ Do not make any electrical connections to pins 2, 4, 6, 8, 10, 34, and 58 through 60.
Table 4-11 lists the required signal levels for the digital input and output pins in the DAV
interface.
53 Ground 54 N.C.
55 VID_RET 56 N.C.
57 VID_RET 58 N.C.
59 N.C. 60 N.C.
Table 4-10 Descriptions of the signals on the DAV connector
Signal name Signal description
LLC_OUT Clock reference signal
FLD YUV directional signal
HS_IN Horizontal reference signal
HS_OUT Horizontal sync signal
LLC_IN Line-locked clock signal
UV(bits 0–7) Digital chrominance data bus
VS_OUT Vertical sync signal
Y(bits 0–7) Digital luminance data bus
Table 4-11 DAV signal levels
Specification Minimum Maximum
Input voltage low –0.3 V 0.8 V
Input voltage high 2.4 V
continued
Table 4-9 Pin assignments on the DAV connector (continued)
Pin number Signal name Pin number Signal name