Specifications

CHAPTER 4
Expansion Features
Second-Level Cache DIMM 51
/AACK Address acknowledge, same as AACK_ signal on PowerPC 603
/ARTRY Address retry, same as ARTRY_ signal on PowerPC 603
/ABB Address bus busy, same as ABB_ signal on PowerPC 603
/CI Cache inhibit, same as CI_ signal on PowerPC 603
/CPU_BG Bus transaction granted, same as BG_ signal on PowerPC 603
/CPU_BR Bus transaction requested, same as BR_ signal on PowerPC 603
/DBB Data bus busy, same as DBB_ signal on PowerPC 603
/GBL Global transaction
/HRESET Main logic board hardware reset
/L2_BG Bus grant to L2 cache; used only in copyback mode
/L2_BR Bus request from L2 cache; used only in copyback mode
/L2_DIS Disables cache when low; contents are invalidated
L2_PRSNT L2 cache present; tied directly to power rail on cache DIMM
/MEM_INHIBIT Indicates L2 cache will source the data for the current cycle; inhibits
main logic board memory controller.
/RSRV Reservation signal, same as RSRV_ signal on PowerPC 603
Reserved DO NOT USE
SHD Share
/SRESET Soft reset, same as SRESET_ signal on PowerPC 603
SYS_CLK System clock, same as SYSCLOCK signal on PowerPC 603
/TA Transfer acknowledge, same as TA_ signal on PowerPC 603
/TBST Transfer burst in progress, same as TBST_ signal on
PowerPC 603
TC(0-1) Transfer code, same as TC signal on PowerPC 603
/TEA Transfer error acknowledge, same as TEA_ signal on PowerPC 603
/TS Transfer start signal, same as TS_ signal on PowerPC 603
TSIZ (0-2) Transfer size for the data transaction
TTYPE(0-4) Transfer type, same as TT signal on PowerPC 603
/WT Write-thru, same as WT_ signal on PowerPC 603
Table 4-7 Signal descriptions for the L-2 cache DIMM connector (continued)
Signal name Description