Specifications

CHAPTER 4
Expansion Features
50 Second-Level Cache DIMM
Table 4-7 defines the signals on the L-2 cache DIMM connector.
21 /L2_BR 61 +3.3 V 101 /TBST 141 SHD
22 /L2_BG 62 D15 102 GND 142 D47
23 TC0 63 D14 103 /CI 143 D46
24 TC1 64 D13 104 /RSRV 144 GND
25 +3.3 V 65 D12 105 Reserved 145 D45
26 /HRESET 66 D11 106 /MEM_INHIBIT 146 D44
27 /TEA 67 +5 V 107 /AACK 147 D43
28 /TS 68 D10 108 GND 148 D42
29 GND 69 D9 109 /TA 149 D41
30 SYS_CLK 70 D8 110 /ARTRY 150 GND
31 +3.3 V 71 D7 111 /ABB 151 D40
32 A31 (LSB) 72 D6 112 A30 152 D39
33 A29 73 +5 V 113 A28 153 D38
34 A27 74 D5 114 GND 154 D37
35 A25 75 D4 115 A26 155 D36
36 A23 76 D3 116 A24 156 GND
37 +3.3 V 77 D2 117 A22 157 D35
38 A21 78 D1 118 A20 158 D34
39 A19 79 +5 V 119 A18 159 D33
40 A17 80 D0 (MSB) 120 GND 160 D32
Table 4-7 Signal descriptions for the L-2 cache DIMM connector
Signal name Description
+5 V Power supply voltage of +5 volts for tag RAM (5% tolerance)
+ 3.3 V Power supply voltage of +3.3 volts for data RAM (5% tolerance)
GND Ground
A(0-31) Processor address bus signals 0 through 31
D(0-63) Processor data bus signals 0 through 63; sampled on the rising edge
of the CLK signal during a write cycle
continued
Table 4-6 Pin and signal assignments for the L-2 cache DIMM connector (continued)
Pin Signal name Pin Signal name Pin Signal name Pin Signal name