Specifications

CHAPTER 4
Expansion Features
Second-Level Cache DIMM 49
Second-Level Cache DIMM 4
The Macintosh Performa 6400 computer has a slot for a second-level (L2) cache on a
DIMM.
The L2 cache DIMM contains the cache controller, tag, and data-store memory. It is a
lookaside cache, which is connected to the PowerPC processor bus. Several signals are
also included to control cache operation. These signals include /L2_DIS,
/MEM_INHIBIT, /L2_BR, /L2_BG, and L2_PRSNT.
Table 4-6 shows the pin and signal assignments on the L2 cache DIMM connector.
Table 4-6 Pin and signal assignments for the L-2 cache DIMM connector
Pin Signal name Pin Signal name Pin Signal name Pin Signal name
1 +5 V 41 A15 81 D63 (LSB) 121 A16
2 D31 42 A13 82 D62 122 A14
3 D30 43 +3.3 V 83 D61 123 A12
4 D29 44 A11 84 GND 124 A10
5 D28 45 A9 85 D60 125 A8
6 D27 46 A7 86 D59 126 GND
7 +5 V 47 A5 87 D58 127 A6
8 D26 48 A3 88 D57 128 A4
9 D25 49 +3.3 V 89 D56 129 A2
10 D24 50 A1 90 GND 130 A0 (MSB)
11 D23 51 /WT 91 D55 131 /DBB
12 D22 52 /GBL 92 D54 132 GND
13 +5 V 53 Reserved 93 D53 133 /CPU_BG
14 D21 54 /SRESET 94 D52 134 /CPU_BR
15 D20 55 +3.3 V 95 D51 135 L2_PRSNT
16 D19 56 TTYPE0 96 GND 136 Reserved
17 D18 57 TTYP1 97 D50 137 TSIZ0
18 D17 58 TTYPE2 98 D49 138 GND
19 +5 V 59 TTYPE3 99 D48 139 TSIZ1
20 D16 60 TTYPE4 100 /L2_DIS 140 TSIZ2
continued