Specifications

CHAPTER 4
Expansion Features
RAM DIMMs 47
Table 4-5 shows how the address signals to the RAM devices are multiplexed during the
row and column address phases for noninterleaved banks.
IMPORTANT
The PSX DRAM controller on the main logic board of the Macintosh
Performa 6400 computer does not provide support for 4 M by 4 bits (12
by 10 addressing) or 1 M by 16 bits (12 by 8 addressing) DRAM
devices. ▲
RAM Devices 4
The memory controller in the PSX IC supports 1 MB, 4 MB, and 16 MB DRAM devices.
The access time (T
RAS
) of the DRAM devices is 70 ns or faster.
Note
The computer supplies +5 volts at VCC on the RAM expansion slot for
DRAM DIMMs. Power for DRAM devices that require 3.3 volts is not
supplied on the RAM expansion slot. ◆
RAM Refresh 4
The PSX IC provides a CAS-before-RAS refresh cycle every 15.6 µs. DRAM devices must
be compatible with this refresh cycle; for example, this cycle will refresh 2K-refresh parts
within 32 milliseconds.
RAM DIMM Dimensions 4
Figure 4-1 shows the dimensions of the RAM DIMM.
IMPORTANT
The JEDEC MO-161 specification shows three possible heights for the
8-byte DIMM. For Power Macintosh computers, developers should use
only the shortest of the three: 1.100 inches. Taller DIMMs put excessive
pressure on the DIMM sockets due to possible mechanical interference
inside the case. ▲
Table 4-5 Address multiplexing in noninterleaved banks
Individual signals on the DRAM_ADDR bus
A(11) A(10) A(9) A(8) A(7) A(6) A(5) A(4) A(3) A(2) A(1) A(0)
Row address 22 23 21 20 19 18 17 16 15 14 13 12
Column address 24 22 11 10 9876543