Specifications

CHAPTER 2
Architecture
Block Diagram and Main ICs 17
The PCI bus bridge in the PSX IC runs asynchronously so that the processor bus and the
PCI bus can operate at different rates. The processor bus operates at a clock rate of
40 MHz and the PCI bus operates at 33 MHz.
The PCI bus bridge generates PCI parity as required by the PCI bus specification, but it
does not check parity or respond to the parity error signal.
Big-Endian and Little-Endian Bus Addressing 2
Byte order for addressing on the processor bus is big endian, and byte order on the PCI
bus is little endian. The bus bridge performs the appropriate byte swapping and address
transformations to translate between the two addressing conventions. For more
information about the translations between big-endian and little-endian byte order, see
Part One, “The PCI Bus,” in Designing PCI Cards and Drivers for Power Macintosh
Computers.
Processor Bus to PCI Bus Transactions 2
Transactions from the processor bus to the PCI bus can be either burst or non burst. Burst
transactions are always 32 bytes long and are aligned on cache-line or 8-byte boundaries.
In burst transactions, all the bytes are significant. Burst transactions are used by the
microprocessor to read and write large memory structures on PCI devices.
Note
For the processor to generate PCI burst transactions, the address space
must be marked as cacheable. Refer to Macintosh Technote Number 1008,
Understanding PCI Bus Performance, for details. ◆
Non burst transactions can be of arbitrary length from 1 to 8 bytes and can have any
alignment. Non burst transactions are used by the processor to read and write small data
structures on PCI bus devices.
PCI Bus to Processor Bus Transactions 2
For transactions from the PCI bus to the processor bus, the bridge responds only to PCI
bus memory commands and configuration commands. On the processor bus, the bridge
generates a burst transaction or a non burst transaction depending on the type of
command and the address alignment. For Memory Write and Invalidate commands that
are aligned with the cache line, the bridge generates a burst write transaction. Similarly,
for Memory Read Line and Memory Read Multiple commands whose alignment is less
than three-quarters through a cache line, the bridge generates a burst read transaction.
The maximum burst read or burst write transaction allowed by the bridge is 32 bytes—8
PCI beats.
Commands other than those mentioned here are limited to two beats if aligned to a
processor bus doubleword boundary and to one beat otherwise.
O’Hare IC 2
The O’Hare IC is based on the Grand Central IC present in the Power Macintosh 7500
computer. It is an I/O controller and DMA engine for Power Macintosh computers using