Specifications

CHAPTER 2

Architecture

16 Block Diagram and Main ICs

System RAM 2

The Macintosh Performa 6400 computer has 8 MB of DRAM memory soldered on the

main logic board. All RAM expansion is provided by DRAM devices on 8-byte

JEDEC-standard DIMMs (dual inline memory modules). Two 168-pin DIMM sockets are

used for memory expansion. Available DIMM sizes are 8, 16, 32, and 64 MB. The DIMM

sockets support both single- and double-sided DRAM modules. The PSX custom IC

provides memory control for the system RAM.

Custom ICs 2

The architecture of the Macintosh Performa 6400 computer is designed around ﬁve large

custom integrated circuits:

■ the PSX memory controller and PCI bridge

■ the O’Hare I/O subsystem and DMA engine

■ the AWACS sound processor

■ the Cuda ADB controller

■ the Valkyrie-AR video subsystem

The computer also uses several standard ICs that are used in other Macintosh

computers. This section describes only the custom ICs.

PSX IC 2

The PSX IC functions as the bridge between the PowerPC 603e microprocessor and the

PCI bus. It provides buffering and address translation from one bus to the other.

The PSX IC also provides the control and timing signals for system cache, ROM, and

RAM. The memory control logic supports byte, word, long word, and burst accesses to

the system memory. If an access is not aligned to the appropriate address boundary, PSX

generates multiple data transfers on the bus.

Memory Control 2

The PSX IC controls the system RAM and ROM and provides address multiplexing and

refresh signals for the DRAM devices. For information about the address multiplexing,

see “RAM Address Multiplexing” on page 46.

PCI Bus Bridge 2

The PSX IC acts as a bridge between the processor bus and the PCI expansion bus,

converting signals on one bus to the equivalent signals on the other bus. The PCI bridge

functions are performed by two converters. One accepts requests from the processor bus

and presents them to the PCI bus. The other converter accepts requests from the PCI bus

and provides access to the RAM and ROM on the processor bus.