Specifications

CHAPTER 2
Architecture
14 Block Diagram and Main ICs
This chapter describes the architecture of the Macintosh Performa 6400 computer. It
describes the major components of the main logic board: the microprocessor, the custom
ICs, and the display RAM. It also includes a simplified block diagram.
Block Diagram and Main ICs 2
The architecture of the Macintosh Performa 6400 computer is based on the PowerPC
603e. Figure 2-1 shows the system block diagram. The architecture of the Macintosh
Performa 6400 computer is based on two buses: the processor bus and the PCI bus. The
processor bus connects the microprocessor, video, cache, and memory; the PCI bus
connects the expansion slots and the I/O devices.
PowerPC 603e Microprocessor 2
The Macintosh Performa 6400 computer uses a PowerPC 603e microprocessor running at
160, 180, and 200 MHz. The principle features of the PowerPC 603e microprocessor
include
■ full RISC processing architecture
■ parallel processing units: two integer and one floating point
■ a branch manager that can usually implement branches by reloading the incoming
instruction queue without using any processing time
■ an internal memory management unit (MMU)
■ 32 KB of on-chip cache memory (16 KB each for data and instructions)
For complete technical details, see the Motorola PowerPC 603 RISC Microprocessor User’s
Manual. This book is listed in “Supplemental Reference Documents,” in the preface.
Memory Subsystem 2
The memory subsystem of the Macintosh Performa 6400 computer consists of ROM and
an optional second-level (L2) cache, in addition to the internal cache memory of the
PowerPC 603e microprocessor. The PSX custom IC provides burst mode control to the
cache and ROM.
ROM 2
The ROM consists of 4 MB of masked ROM soldered to the main logic board.
Second-Level Cache (Optional) 2
The optional second-level (L2) cache consists of 256 KB of high-speed RAM on a 160-pin
DIMM card, which is plugged into a 160-pin edge connector on the main logic board.