User`s manual

3-6-3 PCI Timing Settings

Phoenix – AwardBIOS CMOS Setup Utility

PCI Timing Settings

Item Help

PCI Master 0 WS Write Enabled

PCI Delay Transaction Enabled

Vlink Mode Selection By Auto

Vlink 8X Support Enabled

Menu Level >>

↑↓→←

Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help

F5:Previous Values F6:Optimized Defaults F7:Standard Defaults

PCI Delay Transaction

The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.

Select Enabled to support compliance with PCI specification version 2.1. The settings are:

Enabled and Disabled.

3-7 Integrated Peripherals

Phoenix – AwardBIOS CMOS Setup Utility

Integrated Peripherals

Item Help

> Onboard IDE Function Press Enter

> Onboard Device Function Press Enter

> Onboard Super IO Function Press Enter

Init Display First PCI Slot

Menu Level >>

↑↓→←

Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help

F5:Previous Values F6:Optimized Defaults F7:Standard Defaults

Onboard IDE Function

Please refer to section 3-7-1

Onboard Device Function

Please refer to section 3-7-2

Onboard Super IO Function

Please refer to section 3-7-3

Init Display First

This item allows you to decide to activate whether PCI Slot or AGP VGA first. The settings are:

PCI Slot, AGP Slot.