User`s manual

36
3-6-1 DRAM Timing Settings
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Setting
Item Help
Auto Configuration By SPD
x RAS Active Time 8T
x RAS to CAS Delay 3T
x RAS Percharge Time 3T
x DRAM CAS Latency Time 2.5
x Bank Interleave Disabled
DRAM Command Rate 2T Command
Menu Level >>
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
RAS Active Time
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T and 3T.
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before DRAM
refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast gives faster
performance; and Slow gives more stable performance. This field applies only when synchronous
DRAM is installed in the system. The settings are: 2T, 3T and 4T.
DRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the
DRAM timing. The settings are: 2T and 2.5T.
3-6-2 AGP Timing Settings
Phoenix – AwardBIOS CMOS Setup Utility
AGP Timing Settings
Item Help
AGP Aperture Size 128M
AGP 3.0 Mode 8X
AGP Driving Control Auto
* AGP Driving Value DA
AGP Fast Write Disabled
AGP 3.0 Calibration cycle Enabled
DBI Output for AGP Trans. Disabled
AGP Master 1 WS Write Enabled
AGP Master 1 WS Read Enabled
DBI Output for Frame Trans. Disabled
** PCI Express relative items **
Maximum Payload Size 4096
Menu Level >>
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Note: Change these settings only if you are familiar with the chipset.