User`s manual

4.3 dc Power Distribution
As shown in Figure 4–3, the +12 V dc, –12 V dc, and –5 V dc are supplied to
ISA connectors J19, J20, and J21. The +12 V dc and –12 V dc are supplied
to ISA connectors and PCI32 connectors J24 and J25. The +12 V dc is also
supplied to the CPU fan connector J30, auxiliary fan connector pins on header
J2, and to the flash ROM write-enable conector J14. Vdd is supplied to ISA
connectors, PCI32 connectors and most of the board’s integrated circuits. The
+3 V dc is supplied to the 21164 microprocessor.
4.4 PCI Devices
The EB164 uses the PCI bus as the main I/O bus for the majority of peripheral
functions. The board implements the ISA bus as an expansion bus for system
support functions and relatively slow peripheral devices.
The PCI bus supports multiplexed, burst mode, read and write transfers.
It supports synchronous operation of between 25 MHz and 33 MHz. It also
supports either a 32-bit or 64-bit data path with 32-bit device support in
the 64-bit configuration. Depending upon the configuration and operating
frequencies, the PCI bus supports anywhere between 100MB/s (25-MHz, 32-bit)
to 264MB/s (33-MHz, 64-bit) peak throughput. The PCI provides parity on
address and data cycles. Three physical address spaces are supported:
1. 32-bit memory space
2. 32-bit I/O space
3. 256-byte-per-agent configuration space
The bridge from the 21164 system bus to the 64-bit PCI bus is provided by the
CIA chip. It generates the required 32-bit PCI address for 21164 I/O accesses
directed to the PCI. It also accepts 64-bit double address cycles and 32-bit
single address cycles. However, the 64-bit address support is subject to some
constraints.
Functional Description 4–7