User`s manual

4.1 PCI Interrupts and Arbitration
Table 4–2 PCI-to-ISA SIO Bridge Interrupts
Priority Label Controller Internal/External Interrupt Source
1 IRQ0 1 Internal Internal timer 1
2 IRQ1 1 External Keyboard
3–10 IRQ2 1 Internal Interrupt from controller 2
3 IRQ8#
1
2 External Reserved
4 IRQ9 2 External ISA bus pin B04
5 IRQ10 2 External ISA bus pin D03
6 IRQ11 2 External ISA bus pin D04
7 IRQ12 2 External Mouse
8 IRQ13 2 External Reserved
9 IRQ14 2 External IDE
10 IRQ15 2 External ISA bus pin D06
11 IRQ3 1 External 87312 combination controller
12 IRQ4 1 External 87312 combination controller
13 IRQ5 1 External 87312 combination controller
14 IRQ6 1 External 87312 combination controller
15 IRQ7 1 External 87312 combination controller
1
The # symbol indicates an active low signal.
Interrupt PLDs Function
The MACH210A PLD is an 8-bit I/O slave on the ISA bus at hex addresses
804, 805, and 806. This is accomplished by a decode of the three ISA address
bits sa<2:0> and the three ecas_addr<2:0> bits.
Each interrupt can be individually masked by setting the appropriate bit in the
mask register. An interrupt is disabled by writing a 1 to the desired position
in the mask register. An interrupt is enabled by writing a 0. For example,
bit <7> set in interrupt mask register 1 indicates that the INTB2 interrupt is
disabled. There are three mask registers located at ISA addresses 804, 805,
and 806.
An I/O read transaction at ISA addresses 804, 805, and 806 returns the state of
the 17 PCI interrupts rather than the state of the masked interrupts. On read
transactions, a 1 means that the interrupt source shown in Figure 4–2 has
asserted its interrupt. The mask register can be updated by writing addresses
804, 805, or 806. The mask register is write-only.
4–4 Functional Description