Specifications

17 January 1997 – Subject to Change
System Address Mapping A–25
21164 Address Space
Note:
If a quadword access is specified for the configuration cycle, then the
least significant bit (LSB) of the register number field, ad<2>, must be
zero. A quadword read/write transaction must access quadword-aligned
registers.
If the PCI cycle is a configuration read or write cycle, but ad<1:0> equals 01
2
(like a
Type 1 transfer), then a device on an hierarchical bus is being selected using a
PCI–PCI bridge. This cycle is accepted by the PCI–PCI bridge for propagation to its
secondary PCI bus. During this cycle, ad<23:16> selects a unique bus number;
ad<15:8> selects a device on that bus (typically decoded by the PCI–PCI bridge to
generate the secondary PCI address pattern for IDSEL); and ad<7:2> selects a
longword in the device’s configuration space.
Each PCI–PCI bridge can be configured by PCI configuration cycles on its primary
PCI interface. Configuration parameters in the PCI–PCI bridge will identify the bus
number for its secondary PCI interface, and a range of bus numbers that can exist
hierarchically behind it.
If the bus number of the configuration cycle matches the bus number of the PCI–PCI
bridge secondary PCI interface, it will accept the configuration cycle, decode it, and
generate a PCI configuration cycle with address bits <1:0> = 00
2
on its secondary
PCI interface.
If the bus number is within the range of bus numbers that may exist hierarchically
behind its secondary PCI interface, the PCI–PCI bridge passes on the unmodified
PCI configuration cycle (address bits <1:0> = 01
2
). It will be accepted by a bridge
further downstream. The IDSEL lines are significant in Type 0 configuration cycles.
A.3.4.2 PCI Special/Interrupt Acknowledge Cycles
PCI special/interrupt acknowledge cycle addresses are located in the range
87.2000.0000 to 87.3FFF.FFFF.
The special-cycle command provides a simple message broadcasting mechanism on
the PCI.
The special cycle contains no explicit destination address, but is broadcast to all
devices. The CIA will drive all zeros as the special-cycle address. Each receiving
device must determine if the message contained in the data field is applicable to it.
A write transaction to address range 87.2000.0000 to 87.3FFF.FFFF causes a special
cycle write transaction on the PCI. The 21164 write data will be passed unmodified
to the PCI. Software must write the data in longword 0 of the hexword within the
following fields: