Specifications

A–24 System Address Mapping

Subject to Change – 17 January 1997

21164 Address Space

A.3.4.1 Device Select (IDSEL)

Peripherals are selected during a PCI configuration cycle if the following three

statements are true:

•

Their IDSEL pin is asserted.

•

The PCI bus command indicates a configuration read or write transaction.

•

Address bits <1:0> are 00.

Address bits <7:2> select a longword register in the peripheral’s 256-byte

configuration address space. Transactions can use byte masks.

Peripherals that integrate multiple functional units (like SCSI and Ethernet) can

provide configuration space for each function. Address bits ad<10:8> can be

decoded by the peripheral to select one of eight functional units. Address bits

ad<31:11> are available to generate the IDSEL signals. (Note that IDSELs behind a

PCI–PCI bridge are determined from the device field encoding of a Type 1 access.)

The IDSEL pin of each device corresponds to a unique PCI address bit from

ad<31:11>. The binary value of addr<20:16> is used to select an address that is

asserted on ad<31:11>, as listed in Table A–7.

No device selected.

Table A–7 Generating IDSEL Pin Signals

addr<20:16> ad<31:11>–IDSEL

00000 0000 0000 0000 0000 0000 1

00001 0000 0000 0000 0000 0001 0

00010 0000 0000 0000 0000 0010 0

00011 0000 0000 0000 0000 0100 0

..... .... .... .... .... .... .

10011 0100 0000 0000 0000 0000 0

10100 1000 0000 0000 0000 0000 0

10101 0000 0000 0000 0000 0000 0

..... .... .... .... .... .... .

11111 0000 0000 0000 0000 0000 0