Specifications

A–22 System Address Mapping
Subject to Change – 17 January 1997
21164 Address Space
Software must program CFG before running a configuration cycle. Sparse address
decoding is used.
Note:
The CIA uses CFG<1:0> instead of unused addr<38:35> to be
compatible with the Digital Semiconductor 21071 core logic chipset.
The Digital Semiconductor 21071 core logic chipset is used with Alpha
21064 series microprocessors.
The configuration space address is assembled as follows:
•
The high-order PCI address bits ad<31:24> are always zero.
•
Address bits addr<28:7> correspond to PCI ad<23:2> and provide the
configuration command information (which device to select).
•
Address bits addr<6:3> are used to generate both the length of the PCI
transaction in bytes and the byte enables, as shown in Table A–6.
•
Address bits ad<1:0> are obtained from CFG<1:0>