Specifications

17 January 1997 – Subject to Change
System Address Mapping A–21
21164 Address Space
A.3.4 PCI Configuration Space
PCI configuration space is located in the address range: 87.0000.0000 to
87.1FFF.FFFF. Software designers are advised to clear
CIA_CTRL[FILL_ERR_EN] when probing for PCI devices using configuration
space read transactions. This will prevent the CIA from generating an ECC error if
no device responds to the configuration cycle and UNPREDICTABLE data is read
from the PCI bus.
A 21164 read or write access to this address space causes a configuration read or
write cycle on the PCI. The two types of targets selected, depending upon the value
of the configuration register (CFG), are listed here and shown in Figure A–12.
•
Type 0—These are targets on the primary 64-bit 21164 system PCI bus. These
are selected by making CFG<1:0> equal to 00
2
.
•
Type 1—These are targets on the secondary 32-bit 21164 system PCI bus (that
is, behind a PCI–PCI bridge). These are selected by making CFG<1:0> equal to
01
2
.
Note:
CFG<1:0> equal to 10
2
and 11
2
are reserved by the PCI specification.
Figure A–12 PCI Configuration Space Definition
000111MBZ1
313234353839 29 28 21 20 16 15 13 12 07 06 05 04 03 02
Length
CFG<1:0>
Type 0 PCI
Configuration
Address
CPU Address
Type 1 PCI
Configuration
Address
00
LJ04270A.AI5
000000 Bus Device Function Register 0 100
31 27 26 24 23 16 15 11 10 0708 02 01 00
Byte Offset
31 11 10 0708 02 01 00
IDSEL Function Register 0 0