Specifications

17 January 1997 – Subject to Change
ix
B–5
SIO Bridge Operating Register Address Space Map. . . . . . . . . . . . . . . .
B–6
B–6
Flash ROM Memory Addresses (Within Segment) . . . . . . . . . . . . . . . . .
B–10
B–7
Map of Flash ROM Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–11
B–8
Flash ROM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–12
B–9
Address Bits and PCI Device IDSEL Pins. . . . . . . . . . . . . . . . . . . . . . . .
B–13
B–10
SIO Bridge Configuration Address Space Map . . . . . . . . . . . . . . . . . . . .
B–13
B–11
CIA Control, Diagnostic, and Error Registers . . . . . . . . . . . . . . . . . . . . .
B–15
B–12
CIA Memory Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–16
B–13
PCI Address Translation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–17
B–14
21164 Cache Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .
B–20
C–1
Output Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C–2
C–2
Special Header Entry Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C–6