Specifications

17 January 1997 – Subject to Change
System Address Mapping A–15
21164 Address Space
The high-order PCI address bits ad<31:26> are obtained from either the hardware
address extension register (HAE_MEM) or the 21164 address, depending on sparse
space regions, as shown in Table A–4.
The HAE_MEM register is located in the CIA chip. Figure A–7, Figure A–8, and
Figure A–9 show mapping for the three regions.
1
Missing entries (such as word size with
addr<6:5>
= 11
2
cause UNPREDICTABLE results.
2
In PCI sparse memory space,
ad<1:0>
is always equal to zero.
3
Byte enable set to zero indicates that the byte lane carries meaningful data.
1
Region 1 is 80.0000.0000 to 83.FFFF.FFFF.
Region 2 is 84.0000.0000 to 84.FFFF.FFFF.
Region 3 is 85.0000.0000 to 85.7FFF.FFFF.
Longword
11
00 LDL, STL addr<7>,00 0000 <3:0>
Quadword
11
11 LDQ, STQ 000 0000 <7:0>
Table A–4 HAE_MEM High-Order Sparse Space Bits
Region
1
PCI Address
<31> <30> <29> <28> <27> <26>
1
HAE_MEM
<31>
HAE_MEM
<30>
HAE_MEM
<29>
21164<33> 21164<32> 21164<31>
2
HAE_MEM
<15>
HAE_MEM
<14>
HAE_MEM
<13>
HAE_MEM
<12>
HAE_MEM
<11>
21164<31>
3
HAE_MEM
<7>
HAE_MEM
<6>
HAE_MEM
<5>
HAE_MEM
<4>
HAE_MEM
<3>
HAE_MEM
<2>
Table A–3 (Continued) PCI Memory Sparse Space Read/Write Encodings
Size Byte Offset 21164 PCI
Data-In
Register
addr<4:3> addr<6:5>
1
Instruction ad<2:0>
2
Byte
3
Enable
Byte Lanes
[7:0]