Specifications

A–14 System Address Mapping
Subject to Change – 17 January 1997
21164 Address Space
Table A–3 defines the low-order PCI sparse memory address bits. Address bits
addr<7:3> are used to generate the length of the PCI transaction in bytes, the byte
enables, and ad<2:0>. Address bits addr<30:8> correspond to the quadword PCI
address and are sent out on the PCI as ad<25:3>.
1
All other
int4_valid_h<3:0>
patterns cause UNPREDICTABLE results.
2
Only one STQ case is allowed.
Table A–2 int4_valid_h<3:0> and addr<4:3> for Sparse Space Write
Transactions
21164 Data Cycle int4_valid_h<3:0>
1
addr_h<4:3>
First 0001 0010 0100 1000 00 00 01 01
Second 0001 0010 0100 1000
1100 (STQ)
2
10 10 11 11 11
Table A–3 PCI Memory Sparse Space Read/Write Encodings
Size Byte Offset 21164 PCI
Data-In
Register
addr<4:3> addr<6:5>
1
Instruction ad<2:0>
2
Byte
3
Enable
Byte Lanes
[7:0]
Byte
00
00
01
10
11
LDL, STL addr<7>,00 1110
1101
1011
0111
<0>
<1>
<2>
<3>
Word
01
00
01
10
LDL, STL addr<7>,00 1100
1001
0011
<1:0>
<2:1>
<3:2>
Tribyte
10
00
01
LDL, STL addr<7>,00 1000
0001
<2:0>
<3:1>