Specifications

17 January 1997 – Subject to Change
System Address Mapping A–13
21164 Address Space
entries in Table A–3, such as word size with address addr<6:5> = 11). The
hardware will complete the reference, but the reference is not required to
produce any particular result nor will the CIA report an error.
•
Software must use longword load or store instructions (LDL/STL) to perform a
reference that is of longword length or less on the PCI bus.
– The bytes to be transferred must be positioned within the longword in the
correct byte lanes as indicated by the PCI byte enable.
– The hardware will do no byte shifting within the longword.
•
Quadword load and store instructions (LDQ/STQ) must be used only to perform
quadword transfers. Use of LDQ/STQ instructions for any other references will
produce UNPREDICTABLE results.
•
Read-ahead (prefetch) is not performed in sparse space by the CIA hardware
because the read-ahead might have unwanted side effects.
•
Programmers are required to insert memory barrier (MB) instructions between
sparse space accesses to prevent collapsing in the 21164 write buffer. However,
this is not always necessary. For instance, consecutive sparse space addresses
will be separated by 32 bytes (and will not be collapsed by the 21164
microprocessor).
•
Programmers are required to insert MB instructions if the sparse space address
ordering/coherency to a dense space address is to be maintained.
•
On read transactions, the 21164 microprocessor sends out addr<4:3> indirectly
on the int4_valid_h<3:0>.
•
Accesses with addr<2:0> nonzero will produce UNPREDICTABLE results.
•
The relationship between int4_valid_h<3:0> and 21164 addr<4:3> for a sparse
space write transaction is shown in Table A–2. The important point is that all
other int4_valid_h<3:0> patterns will produce UNPREDICTABLE results such
as the result of collapsing in the 21164 write buffer or issuing an STQ instruction
when an STL instruction was required.