Specifications

A–12 System Address Mapping
Subject to Change – 17 January 1997
21164 Address Space
Address generation in dense space is described in the following list:
•
addr<31:5> is directly sent out on the PCI as ad<31:5>.
•
addr<4:2> is not sent from the 21164 microprocessor, but is inferred from
int4_valid_h<3:0>.
•
ad<4:3> is a copy of addr<4:3>.
•
ad<2> differs for read and write transactions as follows:
– For a read transaction, ad<2> is zero (minimum read resolution in non-
cached space is a quadword).
– For a write transaction, ad<2> equals addr<2>.
A.3.2 PCI Sparse Memory Space
The CIA supports three regions of contiguous 21164 address space that maps to PCI
sparse memory space. The total 21164 range is from 80.0000.0000 to
85.7FFF.FFFF. Sparse address space maps a large piece of 21164 memory address
space to a small PCI address space. For example, a 32-byte memory address might
map to a single-byte PCI address.
A problem arises because the Alpha instruction set can express only ALIGNED
longword and quadword data references. The PCI bus requires the ability to express
byte, word, tribyte, longword, and quadword references. The CIA must also be able
to emulate PCI transactions for PCI devices designed for systems that are capable of
generating the UNALIGNED references.
The CIA accomplishes UNALIGNED PCI references by encoding the size of the
data transfer (byte, word, and so on) and the byte-enable information in the 21164
address. Address bits addr<6:3> are used for this purpose. The PCI longword
address ad<26:3> is generated by using the remaining address bits addr<31:7>.
Quadword address encoding is provided by addr<6:3> with addr<7> assumed to be
zero by the CIA hardware (see Table A–3).
The loss of address bits addr<6:3> has resulted in a 22GB “sparse” address space
that maps to only 704MB of address space on the PCI.
The rules for accessing sparse space are as follows:
•
Sparse space supports all the byte encodings that are expected to be generated in
a system to ensure compatibility with existing and expected PCI devices/drivers.
The results of some references are not explicitly defined (these are the missing