Specifications

17 January 1997 – Subject to Change
System Address Mapping A–11
21164 Address Space
transactions. Valid longwords surrounding invalid longwords (called a “hole”)
are required to be handled correctly by all PCI devices. The CIA will allow such
“holes” to be issued.
•
Read transactions will always be performed as a burst of two or more longwords
on the PCI because the minimum granularity is a quadword. The processor can
request a longword but the CIA will always fetch a quadword, thus prefetching a
second longword. Therefore, this space cannot be used for devices that have read
side effects. Although a longword may be prefetched, the prefetch buffer is not
treated as a cache and thus coherency is not an issue. A quadword read
transaction is not atomic on the PCI, that is, the target device is at liberty to force
a retry after the first longword of data is sent, and then allow another device to
take control of the PCI bus. The CIA does not drive the PCI lock signal and thus
the PCI cannot ensure atomicity. This is true of all current Alpha systems using
the PCI.
•
The 21164 microprocessor merges noncached read transactions up to a 32-byte
maximum. The largest dense space read transaction is thus 32 bytes from the
PCI bus.
•
Write transactions to this space are buffered in the 21164 microprocessor. The
CIA supports a burst length of 8 on the PCI, corresponding to 32 bytes of data. In
addition, the CIA provides four 32-byte write buffers to maximize I/O write
performance. These four buffers are strictly ordered.
Address generation in dense space is shown in Figure A–6.
Figure A–6 Dense Space Address Generation
LJ04264A.AI5
1
1
21164 Address
<31:5>
PCI Dense
Memory
Address
0 0
21164
int4_valid
0 0
31 05 04 02 01 00
34 33 32 31 05 04 02 01 00
39 38
35
10