Specifications

A–2 System Address Mapping
Subject to Change – 17 January 1997
21164 Address Space Configuration Supported by the CIA
Figure A–1 21164 Address Space
A.2 21164 Address Space Configuration Supported by the CIA
As shown in Figure A–2, the CIA supports only the first 8GB of cacheable memory
space; the remainder is reserved. The cacheable memory space block size is fixed at
64 bytes. The CIA will send READ and FLUSH commands to the 21164 caches for
DMA traffic to the 8GB memory address area.
The CIA supports 21164 access to memory-mapped I/O devices in noncacheable
address space. The CIA defines the following five address spaces within the
noncacheable space:
•
22GB PCI memory sparse space
•
2GB PCI I/O space
•
4GB PCI memory dense space
•
4GB that includes address space for:
– PCI configuration
– Special/interrupt acknowledge cycles
– CIA control and status registers (CSR)
– Flash ROM and support logic registers
•
16GB PCI byte/word I/O space
LJ04259A.AI5
Cached Memory
Reserved
00.0000.0000
01.FFFF.FFFF
02.0000.0000
7F.FFFF.FFFF
80.0000.0000
8B.FFFF.FFFF
Noncacheable Address Space