Specifications

17 January 1997 – Subject to Change
Functional Description 4–21
Serial ROM
4.8 Serial ROM
The serial ROM (SROM) provides the following functions:
•
Initializes the CPU’s internal processor registers (IPRs).
•
Sets up the microprocessor’s internal L1/L2 caches.
•
Performs the minimum I/O subsystem initialization necessary to access the
real-time clock (RTC) and the system’s flash ROM.
•
Detects CPU speed by polling the periodic interrupt flag (PIF) in the RTC.
•
Sets up memory and backup cache (Bcache) parameters based on the speed of
the CPU.
•
Wakes up the DRAMs.
•
Initializes the Bcache.
•
Copies the contents of the entire system memory to itself to ensure good memory
data parity.
•
Scans the system flash ROM for a special header that specifies where and how
the system flash ROM firmware should be loaded.
•
Copies the contents of the system flash ROM to memory and begins code
execution.
•
Passes parameters up to the next level of firmware to provide a predictable
firmware interface.
Figure 4–9 is a simplified diagram of the SROM and serial port logic.
Signal srom_oe_l selects the input to a multiplexer (pc164.3). The multiplexer
selects either the output of the Xilinx XC17128 SROM (real_srom_d) or a user-
supplied input through the test SROM port (test_srom_d). The multiplexer output
(srom_dat_h) provides data input to the 21164 microprocessor.
After the initial SROM code has been read into the 21164 microprocessor’s Icache,
the test SROM port can be used as a software-controlled serial port. This serial port
can be used for diagnosing system problems when the only working devices are the
microprocessor, the SROM, and the circuits needed for the direct support of the
microprocessor and SROM (such as the clock). Connector J32 supports an RS-232
or RS-422 terminal connection to this port by using 1488 and 1489 line driver and
receiver components. Additional external logic is not required.