Specifications

4–18 Functional Description
Subject to Change – 17 January 1997
System Clocks
At system reset, the 21164 microprocessor’s irq_h<3:0> pins are driven by the
clock divisor values set by four jumpers on J30. During normal operation, these
signals are used for interrupt requests. The pins are either switched to ground or
pulled up in a specific combination to set the 21164 microprocessor’s internal
divider. The divisor is programmable and can range from 3 to 15. (Refer to Section
2.1.2 for a list of jumper combinations.)
The 21164 microprocessor produces the divided clock output signal sys_clk_out1
that drives the CDC586 PLL clock-driver chip. This synchronous system clock
provides the system memory and I/O clock reference.
The clock-driver chip is used to minimize system-level clock skew as well as
creating square-wave clocks from what can sometimes be an asymmetrical clock
from the 21164 microprocessor. The clock driver provides a 50% duty-cycle output
clock that is referenced to the 21164 microprocessor’s sys_clk_out1 signal and
aligned with a reference feedback clock. The clock driver is configured (OPT<2:0>
= 011) such that the output frequency equals the input frequency and is in phase. The
PLL provides copies to each DSW chip, the CIA chip, each PCI slot, the PCI-to-ISA
bridge, and the PCI IDE controller. The PLL also synchronizes the arbiter.
The DSW/CIA chipset generates its own 1X and 2X clocks on each ASIC. Each
ASIC uses an integrated PLL together with an onchip clock trunk/buffer scheme to
maintain chip skews under 0.6 ns.
Clock signal pciclk_sio synchronizes the PCI-to-ISA bridge’s PCI bus transactions.
The supported PCI cycle times range from 40 ns (25 MHz) to 30 ns (33.3 MHz).
However, because of the 21164 microprocessor’s speed BIN points, the 33.3-MHz
cycle time will always be used.
A 14.3-MHz frequency generator produces the signal 14mhz_out. This signal is
delivered to the 37C935 combination controller for the diskette data separator and
other I/O clocks. The combination controller produces output clock osc, which is
then delivered to the two ISA slots and the PCI-to-ISA bridge for synchronization.