Specifications

17 January 1997 – Subject to Change
Functional Description 4–15
Interrupts
4.5.1 Interrupt PLD Function
The MACH210A PLD is an 8-bit I/O slave on the ISA bus at hex addresses 804,
805, and 806. This is accomplished by a decode of the three ISA address bits
sa<2:0> and the three ecas_addr<2:0> bits.
Each interrupt can be individually masked by setting the appropriate bit in the mask
register (see Figure 4–6). An interrupt is disabled by writing a 1 to the desired
position in the mask register. An interrupt is enabled by writing a 0. For example, bit
<1> set in interrupt mask register 1 indicates that the INTB2 interrupt is disabled.
There are three mask registers located at ISA addresses 804, 805, and 806.
An I/O read transaction at ISA addresses 804, 805, and 806 returns the state of the 18
PCI interrupts rather than the state of the masked interrupts. On read transactions, a 1
means that the interrupt source has asserted its interrupt. The mask register can be
updated by writing addresses 804, 805, or 806. The mask register is write-only.
Figure 4–6 Interrupt/Interrupt Mask Registers
76543210
ISA Address 804
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
ISA Address 805
ISA Address 806
IDE
MK2306-37
INTD0
Reserved
Reserved
INTB0 INTA3 INTA2 INTA1 INTA0SIO
INTC3 INTC2 INTC1 INTC0 INTB3 INTB2 INTB1
Reserved Reserved Reserved Reserved INTD3 INTD2 INTD1