Specifications

17 January 1997 – Subject to Change
Functional Description 4–11
Interrupts
4.4.2 Utility Bus Memory Device
The AlphaPC 164 Ubus drives a flash ROM memory device. The flash ROM chip
provides 1MB of flash memory for operating system support.
Flash data is accessed through 20 address inputs. The low-order 19 address bits are
driven by ISA bus sa<18:0>. The high-order 20th bit (flash_adr19) is driven by the
Ubus decode PLA. Address bit flash_adr19 can be changed by writing to ISA I/O
port x800.
The +12 V is applied to the flash ROM by means of jumper J31 so that code updates
can be accomplished, if desired.
4.4.3 ISA Expansion Slots
Two ISA expansion slots are provided for plug-in ISA peripherals (J33 and J35).
4.5 Interrupts
This section describes the AlphaPC 164 interrupt logic. PCI-, ISA-, and CIA-
generated interrupts are described. Figure 4–5 shows the interrupt logic.
The PCI-to-ISA SIO bridge chip provides the functionality of two 8259 interrupt
control devices. These ISA-compatible interrupt controllers are cascaded such that
14 external and 2 internal interrupts are available. The PCI interrupt acknowledge
command should be used to read the interrupt request vector from the SIO.
However, the AlphaPC 164 system has more external interrupts than the SIO can
handle. Therefore, all the ISA interrupts are sent to the SIO except for the 2 CIA
interrupts, the TOY interrupt, the IDE controller interrupt, and the 16 PCI interrupts.
They are sent to an external interrupt programmable logic array (PLA). This PLA
takes these interrupts, as well as an OR of the nonexistent memory (NMI) and error
signals from the SIO, and generates pci_isa_irq. During reset, cpu_irq<3:0>
convey the system clocking ratios and delays, which are set by jumpers on J30.
Table 4–1 lists each system interrupt, its fixed interrupt priority level (IPL), and its
AlphaPC 164 implementation. Table 4–2 lists each ISA bus interrupt and its
AlphaPC 164 implementation.