Specifications

4–6 Functional Description
Subject to Change – 17 January 1997
PCI Devices
The DSW chip contains the memory interface data path. This includes a 64-byte
victim buffer, a 32-byte I/O read buffer, four 32-byte I/O write buffers, and two
DMA buffers.
The four DSW chips receive data from the CPU by means of the 128-bit CPU data
bus. They transfer data to and from the CIA by means of the 64-bit IOD bus. Any
data directed to or from the PCI bus must be transferred through the CIA. The DSW
chips provide the system with a selectable 128-bit or 256-bit-wide memory path.
Selection is made through jumper J1.
4.2.3 Main Memory Interface
Four DSW chips, along with the CIA, provide a 128-bit or 256-bit-wide, high-speed
memory data path for both CPU memory accesses and PCI DMA. The AlphaPC 164
supports four (128-bit mode) or eight (256-bit mode) DRAM SIMM modules.
Quadword ECC is supported on the DRAM and CPU buses. The same quadword
ECC that is supported by the 21164 microprocessor is also supported on the memory
bus. Byte parity is generated on the PCI bus.
The AlphaPC 164 supports a maximum of 512MB of main memory. In all cases, the
memory is organized as one single bank. Table 1–1 lists total memory and memory
bus width along with the corresponding SIMM sizes required. All CPU cacheable
memory accesses and PCI DMA accesses are controlled and routed to main memory
by the 21172 core logic chipset.
The AlphaPC 164 implements the alternate memory mode for DRAM RAS and CAS
control signals. Alternate memory mode is explained in the Digital Semiconductor
21172 Core Logic Technical Reference Manual. The row and column addresses for
the DRAM SIMMs are partitioned such that any victim’s row address will match its
corresponding read miss row address. This allows a page-mode-write operation to
follow a read operation during read miss/victim processing.
4.3 PCI Devices
The AlphaPC 164 uses the PCI bus as the main I/O bus for the majority of peripheral
functions (see Figure 4–3). The board implements the ISA bus as an expansion bus
for system support functions and for relatively slow peripheral devices.