Specifications

17 January 1997 – Subject to Change
Functional Description 4–5
Digital Semiconductor 21172 Core Logic Chipset
4.2.1 CIA Chip Overview
The CIA application-specific integrated circuit (ASIC) accepts addresses and
commands from the 21164 microprocessor and drives the main memory array with
the address and control signals. It also provides an interface to the 64-bit PCI I/O
bus.
The CIA chip provides the following functions:
•
Serves as the interface between the 21164 microprocessor, main memory
(addressing and control), and the PCI bus. A 3-entry CPU instruction queue is
implemented to capture commands should the memory or I/O port be busy.
•
Provides the DSW chips with control information to direct the data flow.
•
Provides the interface to the PCI bus, and therefore, contains a portion of the
data path. This includes the error correction code (ECC) generation and check
logic for data transfers to and from the DSW chips. It also contains data buffers
for all four transaction types (I/O read and write operations, and direct memory
access (DMA) read and write operations). Each buffer is 64 bytes in size.
•
Generates the row and column addresses for the DRAM SIMMs, as well as all
the memory control signals (RAS, CAS, WE). All the required DRAM refresh
control is contained in the CIA.
•
Provides all the logic to map 21164 noncacheable addresses to PCI address
space, as well as all the translation logic to map PCI DMA addresses to system
memory.
Two DMA conversion methods are supported: direct mapping, where a base offset is
concatenated with the PCI address, and scatter-gather mapping, which maps an 8KB
PCI page to any 8KB memory page. The CIA contains an 8-entry scatter-gather
translation lookaside buffer (TLB), where each entry holds four consecutive page
table entries (PTEs).
Refer to Appendix A for additional details on PCI and DMA address mapping.
4.2.2 DSW Chip Overview
Four DSW ASICs provide the interface between the 128-bit 21164 data bus
(data_h<127:0>) and 16-bit check bus (data_check_h<15:0>), the 288-bit DRAM
memory data bus (mem_dat<287:0>), and the CIA chip for PCI data (iod<63:0>
and iod_ecc<7:0>).