Specifications

4–4 Functional Description
Subject to Change – 17 January 1997
Digital Semiconductor 21172 Core Logic Chipset
Figure 4–2 Main Memory Interface
data_h<127:0>
Data Switch
(X 4)
Control, I/O Interface,
Main Memory Array
DRAM0 DRAM1 DRAM2 DRAM3 DRAM4 DRAM5 DRAM6 DRAM7
mem_dat<143:0> mem_dat<287:144>
addr_bus_req adr_cmd_par cack cmd<3:0> dack fill fill_error fill_id idle_bc int4_valid<3:0> sys_res<1:0> tag_ctl_par tag_dirty victim_pending
cmc<8:0> ioc<<6:0> mem_en
iod<63:0> iod_ecc<7:0>
memadr<11:0>
bnmemadr<11:0>
Buffers
21164
PC164-03
pc164.2
pc164.8-.11
pc164.7
pc164.16
data_check_h<15:0>
addr_h<39:4> System Control*
*
memwe_l
memcas_l<7:0> memrasb_l<7:0> memrasa_l<7:0>
bn_we_l
and Address
64-Bit PCI
I/O Bus
128bit_l
pc164.12 pc164.13 pc164.12 pc164.13 pc164.14 pc164.14 pc164.15 pc164.15
J1