Specifications

4–2 Functional Description
Subject to Change – 17 January 1997
AlphaPC 164 Bcache Interface
4.1 AlphaPC 164 Bcache Interface
The 21164 microprocessor controls the board-level L3 backup cache (Bcache) array
(see Figure 4–1). The data bus (data_h<127:0>), check bus (data_check_h<15:0>),
tag_dirty_h, and tag_ctl_par_h signals are shared with the system interface.
Figure 4–1 AlphaPC 164 L3 Bcache Array
The Bcache is a 1MB, direct-mapped, synchronous SRAM with a 128-bit data path.
It is populated with 9 ns, 32K x 36 static RAMs (SRAMs). In most cases, wave-
pipelined accesses can decrease the cache loop times by one CPU cycle. The Bcache
supports 128-byte or 64-byte transfers to and from memory as dictated by the DSW
chip mode.
21164
index_h<20:4>
idle_bc
Bcache
Data
Array
PC164-02
st_clk1_h
Microprocessor
pc164.5,6pc164.2
data_h<127:0>
tag_data_h<29:20>
tag_valid_h
tag_dirty_h
tag_ctl_par_h
data_check_h<15:0>
tag_data_par_h
tag_data_h<38:30>
SRAM
Tag
Array
(From CIA Chip)
Buffer
pc164.4
data_ram_oe_h
data_ram_we_h
tag_ram_oe_h
tag_ram_we_h
st_clk1_<9:1>_h
index_h<20:6>