Specifications

17 January 1997 – Subject to Change
Index–3
J
Jumper configurations
,
2–4
Jumpers
,
2–3
Bcache size
,
2–6
Bcache speed
,
2–6
boot option
,
2–6
clock divisor
,
2–6
flash ROM update
,
2–7
memory bus width
,
2–5
Mini-Debugger
,
2–6
K
Keyboard
connector pinouts
,
2–11
controller
,
4–9
M
Memory mode
,
4–6
Memory subsystem
,
1–3
Mini-Debugger
,
4–24
Mouse
connector pinouts
,
2–11
controller
,
4–9
N
Numbering convention
,
xiv
O
Operating systems
,
4–25
software support
,
1–7
Ordering information
,
F–1
P
Packaging
chipset
,
4–3
Parallel
port
,
4–9
Parallel bus connector pinouts
,
2–10
PCI
bridge
,
4–8
bus
,
4–6
connector pinouts
,
2–7
speed
,
4–7
configuration address space
,
B–13
dense memory space
,
B–10
devices
,
4–6
expansion slots
,
4–8
interface
,
1–4
sparse I/O space
,
B–1
sparse memory space
,
B–1
window uses
,
A–41
Physical mapping. See Direct mapping.
Power
distribution
,
4–22
monitor
,
4–19
requirements
,
3–1
Power supply
dc ampere requirements
,
3–1
wattage requirements
,
3–1
PTE
,
4–5
,
A–35
R
Ranges
,
xiv
RAS
,
4–5
,
4–6
,
C–4
RO
,
xiii
RW
,
xiii
S
SAC
,
A–32
Scatter-gather
addressing
,
A–35
mapping
,
4–5
,
A–32
TLB hit
,
A–39
TLB miss
,
A–39
Serial ports
,
4–9
Serial ROM. See SROM.
Single address cycle. See SAC.
SIO
,
4–8
,
4–11
address assignments
,
B–6
configuration address space
,
B–13