Specifications

17 January 1997 – Subject to Change
Glossary and Acronyms E–5
RISC
Reduced instruction set computing. A computing system architecture with an
instruction set that is paired down and reduced in complexity so that most
instructions can be performed in a single processor cycle. High-level compilers
synthesize the more complex, least frequently used instructions by breaking them
down into simpler instructions. This approach allows the RISC architecture to
implement a small, hardware-assisted instruction set, thus eliminating the need for
microcode.
Scache
Secondary cache. A 96KB L2 cache reserved for instructions and data on the 21164
microprocessor chip.
SIMM
Single inline memory module.
SRAM
Static random-access memory.
SROM
Serial read-only memory.
UART
Universal asynchronous receiver–transmitter.
word
Two contiguous bytes (16 bits) starting on an arbitrary byte boundary. The bits are
numbered from right to left, 0 through 15.
write-back cache
A cache in which copies are kept of any data in the region. Read and write operations
may use the copies, and write operations use additional states to determine whether
there are other copies to invalidate or update.