Specifications

E–2 Glossary and Acronyms
Subject to Change – 17 January 1997
bus
A group of signals that consists of many transmission lines or wires. It interconnects
computer-system components to provide communications paths for addresses, data,
and control information. The buses used in the AlphaPC 164 include PCI64, PCI32,
and ISA.
cache memory
A small, high-speed memory placed between slower main memory and the
processor. A cache increases effective memory transfer rates and processor speed. It
contains copies of data recently used by the processor and fetches several bytes of
data from memory, anticipating that the processor will access the next sequential
series of bytes. The 21164 microprocessor contains three onchip internal caches, one
8KB L1 cache for instructions, one 8KB L1 cache for data, and one unified 96KB L2
combined instruction and data cache. See also Bcache and write-back cache.
CAS
Column address strobe.
CIA
Control, I/O interface, and address chip. Part of the 21172 core logic chipset.
CMOS
Complementary metal-oxide semiconductor.
Dcache
Data cache. An 8KB L1 cache reserved for data on the 21164 microprocessor chip.
DRAM
Dynamic random-access memory. Read/write memory that must be refreshed (read
from or written to) periodically to maintain the storage of information.
DSW
Data switch chip. Part of the 21172 core logic chipset.